The present invention generally relates to computer architectures, and particularly to a compound superscalar Harvard architecture microprocessor which uses extensive multiplexing and a very wide instruction word format.
A computer which includes the following two characteristics is generally referred to as having a "Harvard" architecture. Namely, the computer will be designed with separate instruction and data stores, and independent buses will be provided to enable the central processing unit ("CPU") of the computer to communicate separately .with each of these stores. This is in contrast to a "yon Neumann" or "Princeton" based computer architecture, which generally employs the same physical store for both instructions and data, and a single bus structure for communication with the CPU. Various approaches have been taken to designing a microcomputer or microprocessor with a Harvard architecture, as represented by the following patents: Yasui et al. U.S. Pat. No. 5,034,887, issued on Jul. 23, 1991, entitled "Microprocessor With Harvard Architecture"; Portanova et al. U.S. Pat. No. 4,992,934, issued on Feb. 12, 1991, entitled "Reduced Instruction Set Computing Apparatus And Methods"; Mehrgardt et al. U.S. Pat. No. 4,964,046, issued on Oct. 16, 1990, entitled "Harvard Architecture Microprocessor With Arithmetic Operations And Control Tasks For Data Transfer Handled Simultaneously"; and Simpson U.S. Pat. No. 4,494,187, issued on Jan. 15, 1985, entitled "Microcomputer With High Speed Program Memory". Additionally, it should be noted that the Intel i860 64-bit microcomputer has been described as having an on-board Harvard architecture, due to the provision of separate instruction and data cache paths. In this regard, a description of the Intel i860 chip design may be found in i860 Microprocessor Architecture, by Neal Margulis, Osborne McGraw-Hill, 1990.
The use of separate instruction and data communication paths in a Harvard architecture machine effectively increases the overall speed of the computer by enabling an instruction to be accessed at the same time that data for this or another instruction is accessed. In the context of programmed operations, the instruction is usually referred to as the "opcode" (the operation code), and the data is referred to as the "operand". While the benefit in speed of using the Harvard architecture is significant, the full potential of a machine based upon the Harvard architecture, has yet to be realized. However, a significant advance in the design of a Harvard architecture computer features the use of an address store for containing an ordered sequence of program memory addresses. The address store (referred to as "queue memory") determines the sequence of operations to be implemented through its stack of program memory addresses. In this regard, each of these program memory addresses identify the location of the first instruction of a particular subroutine which is contained in the program memory. The address store may also contain the address of one or more subroutine arguments which is, in turn, contained in either a value store or in a data memory. Thus, the address store may be utilized as a location server for both the program memory and the data memory of a computer which is based upon the Harvard architecture.
The present invention not only builds upon the advance offered by queue memory, but it also represents a significant departure from prior Harvard architecture computer designs. It this regard, it is a principal objective of the present invention to provide a Harvard architecture based microprocessor which achieves a substantial degree of both design and programming flexibility.
It is another objective of the present invention to provide a Harvard architecture based microprocessor which is capable of performing several operations in a single instruction, including small subroutines.
It is also an objective of the present invention to provide a Harvard architecture based microprocessor which enables a single instruction to make multiple uses of the same computer components in a single clock cycle.
It is a further objective of the present invention to provide a Harvard architecture based microprocessor which employs a very wide instruction word format which completely eliminates the need for microcode decoding or even an instruction register.
It is an additional objective of the present invention to provide a Harvard architecture based microprocessor which employs parallel processing to achieve compound superscalar operations.
It is still another objective of the present invention to provide a Harvard architecture based microprocessor which eliminates inefficiencies that could arise when a branch or jump operation is encountered in pipelined instructions.
It is still a further objective of the present invention to provide a Harvard architecture based microprocessor which avoids a metastable condition in which data changes at the same time as the clock.
It is yet another objective of the present invention to provide a Harvard architecture based microprocessor which is capable of inexpensive implementation in an application specific integrated circuit ("ASIC").